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Run AI Workloads on TPUs

Managed by Google Cloud

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Last updated 13 saat

Welcome to the Run AI workloads on TPUs Course Series, a practical, engineering-focused learning path designed to help you deploy and scale advanced AI workloads on Google's custom silicon with confidence. In this foundational course, TPU Deep Dive, you will explore the core hardware mechanics of the platform, including an in-depth look at the TPU chip and its spatial systolic array architecture, the physics behind various interconnect topologies (2D/3D Torus and Boardfly), the design evolution across eight generations, and the developer mental models required to maximize hardware saturation.

This curriculum is planned to expand rapidly, with a series of specialized courses coming soon to cover the XLA compiler, TorchTPU, distributed training, real-time inference, and the full-scale AI Hypercomputer framework designed specifically through the lens of TPU storage and networking.